assembly - x86 LOCK question on multi-core CPUs -

is true x86 asm "lock" command prefix causes cores freeze while instruction following "lock" being executed?

i read in blog post , doesn't make sense. can't find indicates if true or not.

it's locking memory bus address. the intel 64 , ia-32 architectures software developer's manual - volume 3a: system programming guide, part 1 tells us:

7.1.4 effects of lock operation on internal processor caches.

for intel486 , pentium processors, lock# signal asserted on bus during lock operation, if area of memory being locked cached in processor.

for p6 , more recent processor families, if area of memory being locked during lock operation cached in processor performing lock operation write-back memory , contained in cache line, processor may not assert lock# signal on bus. instead, modify memory location internally , allow [its] cache coherency mechanism insure operation carried out atomically. operation called "cache locking." cache coherency mechanism automatically prevents 2 or more processors have same area of memory simultaneously modifying data in area. (emphasis added)

here learn p6 , newer chips smart enough determine if have block off bus or can rely on intelligent caching. think neat optimization.

i discussed more in blog post "how locks lock?"